CLOCK DATA RECOVERY CIRCUIT AND WIRELESS MODULE INCLUDING SAME

摘要

This clock data recovery circuit (11) is provided with: a ring oscillator (17); an oscillation control circuit unit (15) which starts and stops operation of the ring oscillator (17) depending upon the presence or absence of input of a PWM signal; a counter circuit unit (19) for counting pulse signals and holding an N-bit count value; a register circuit unit (21) which has an M-bit register and is configured so as to be able to transfer the upper M bits among the N-bit count value as a reference count value in response to the input of a transfer signal; a comparator circuit unit (25) which outputs a timing clock if the count number held by the counter circuit unit (19) exceeds the reference count value held by the register circuit unit (21); and a transfer control circuit unit (23) which, in synchronization with the start-up timing of the PWM signal, generates the transfer signal for transferring the reference count value from the counter circuit unit (19) to the register circuit unit (21) and a reset signal for resetting the counter circuit unit (19).