发明名称 LAYOUT METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT AND PROGRAM THEREFOR
摘要 A power domain is automatically generated. A computer performs a function simulation process 9 for evaluating whether or not a designed circuit satisfies a specification, and a clustering process 10 which obtains a power domain by clustering logical blocks in which activation timings are within a range, based on the result of the function simulation process. Since the power domain is obtained by a process performed by the computer, the power domain can be optimized compared to a case when it is obtained by hand (manual work of the designer).
申请公布号 US2012216166(A1) 申请公布日期 2012.08.23
申请号 US201213372434 申请日期 2012.02.13
申请人 RENESAS ELECTRONICS CORPORATION 发明人 SUTO KENTA;SHIBATANI SATOSHI;ISHIKAWA RYOJI;SAITO KEN;INOUE YOSHIO
分类号 G06F17/50 主分类号 G06F17/50
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