DEVICE FOR GENERATING CLOCK SIGNALS FOR ASYMMETRIC COMPARISON OF PHASE ERRORS

摘要

A device for generating a clock signal, including a phase-locked loop including: a controlled oscillator to deliver a clock signal; plural phase comparators to compare a phase of the clock signal delivered by the controlled oscillator with plural clock signal phases applied at an input of the phase-locked loop; a mechanism for weighted summation of output signals of the plural phase comparators such that one or more of the weighting coefficients applied to one of the output signals has an absolute value that overrides the absolute values of the other weighting coefficients applied to the other output signals; and a mechanism filtering the weighted sum of the output signals of the plural phase comparators, to deliver at an output a control signal to the controlled oscillator.