| 摘要 |
<p>Calibration of the timing of the latching of ADC output data The data register 140 latching the output of the ADC 110 should be clocked when the data input to the register is stable in order to avoid capture of erroneous data due to violations of setup or hold time. In a calibration phase, a known input signal is applied to the ADC 110 and the peak amplitude of digital data signals latched by register 140 is detected 170. If the detected peak exceeds a threshold, this indicates nthat the data input was not stable when the register was clocked. The delay of the data input signal or the delay of the clock is adapted by delay controller 160, which controls one or both of the input delay circuit 130 and the clock manager 150 in response to the peak detector in order to provide adequate setup and hold times. The analogue input signal source 102 may be decoupled during calibration so that the effective input signal is generated by thermal noise or other factors within or associated with the ADC 110. Alternatively, a sine signal may be provided by a calibration signal generator 106 or a clock signal may be provided from the clock circuit 150.</p> |
