| 摘要 |
A structure and method for increasing the operating speed and reducing the overall programming time of a memory array are provided herein. The method and structure reduce the maximum write current consumption, for writing a plurality of data bits to a NVM array, by writing the data bits sharing an activated word line at different times (e.g., activating bit lines associated with an activated word line at different times). The write operation of respective data bits, which individually utilize only a fraction of the overall write window of the bits, are interleaved so that the maximum write current of respective bits are offset in time from the maximum write current of another bit, allowing a larger number of data bits to be written without exceeding system specifications (e.g., maximum current) and reducing overall memory write time. |
