| 摘要 |
A B S T R A C T The present invention provides a method of controlling and configuring an avionic system 5 architecture comprising at least one calculation unit CPU (1, 2) and at least one calculation circuit FPGA (3, 4) hosting avionic functions or avionic models and communicating via a digital bus (6), said method being dedicated to optimizing the execution of test function 10 processing, in particular on test benches, by reconfiguring said architecture, if necessary, the method being characterized in that it consists: a) in using a set of execution rules (RI) for the processes executed by the calculation circuits FPGA (3, 15 4) and by the calculation units CPU (1, 2); b) in monitoring pertinent parameters concerning the general state of the avionic system as a function of the execution rules (R1); c) in generating an alert when a parameter does not 20 comply with the execution rules (R1) and according to d) in verifying the alert that has been generated; e) in validating or in invalidating the alert as generated and verified in this way; and f) in reconfiguring the architecture of the avionic 25 system in dynamic and automatic manner in the event of the alert being validated, or according to g) in returning to step a) in the event of the alert being invalidated. Ml Fig.1 EK $ ml r _ _E E rJ/0 M2 FIET a_ b Fig.2 Cg Fig.3 YES f An::hitecture reconfigurto Anticipated reconfiguration ....... ..... rget architecture ready to go |
