发明名称 METHOD FOR EXTRACTING IBIS SIMULATION MODEL
摘要 <P>PROBLEM TO BE SOLVED: To provide a method for easily extracting a highly accurate IBIS simulation model about a semiconductor device in which a plurality of semiconductor chips are incorporated. <P>SOLUTION: The method of extracting an IBIS simulation model includes: a step of performing transistor level circuit simulation by simultaneously treating output transistors of first and second output buffers of first and second semiconductor chips connected to a common external connection terminal as a transistor model, and extracting an AC characteristic model of the first output buffer in an IBIS simulation model; a step of adding output capacities in the transistor level circuit simulation model of the first and second output buffers, and calculating the output capacity model of the first output buffer in the IBIS simulation model; and a step of synthesizing the IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristic model and the output capacity model. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012150718(A) 申请公布日期 2012.08.09
申请号 JP20110009995 申请日期 2011.01.20
申请人 ELPIDA MEMORY INC;HITACHI ULSI SYSTEMS CO LTD 发明人 YOSHIMURA MASAAKI;NISHIO YOJI;NONOYAMA SADAHIRO;MATSUO KOJI;ITANO SHINJI;TANIGAMI YOSHIYUKI
分类号 G06F17/50 主分类号 G06F17/50
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