发明名称 MECHANISM FOR LOW POWER STANDBY MODE CONTROL CIRCUIT
摘要 Embodiments of the invention are generally directed to a low power standby mode control circuit. An embodiment of an apparatus includes a processor, an interface for a connection with a second apparatus, and an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode. The apparatus further includes a standby mode control circuit, the standby control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit.
申请公布号 US2012204048(A1) 申请公布日期 2012.08.09
申请号 US201213362930 申请日期 2012.01.31
申请人 KIM GYUDONG;KIM EUNGU;KIM MIN-KYU;SHIM DAEYUN;SHARMA RAVI;KIM MYOUNGHWAN;LEE JAERYON;SILICON IMAGE, INC. 发明人 KIM GYUDONG;KIM EUNGU;KIM MIN-KYU;SHIM DAEYUN;SHARMA RAVI;KIM MYOUNGHWAN;LEE JAERYON
分类号 G06F1/32 主分类号 G06F1/32
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