| 摘要 |
PURPOSE: A synchronization circuit is provided to reduce delay locked operation time by operating a first loop circuit and a second loop circuit when a phase difference between a clock signal and a feedback signal is minimized. CONSTITUTION: A first delay unit(210) generates a preliminary delay signal by delaying an input signal with delay time corresponding to the first initial delay information. A second delay unit(260) generates a delay signal by delaying a preliminary delay signal with delay time corresponding to the second initial delay information. An initial delay monitoring circuit(600) generates the first initial delay information and the second initial delay information in response to an input signal and an internal delay signal of the first delay unit. |
