发明名称 Packaging an integrated circuit die with backside metallization
摘要 A method (32) of packaging integrated circuit (IC) dies (48) includes applying (36) a laminating material (44) to a wafer (40), and separating (46) the wafer (40) into multiple IC dies (48) such that the laminating material (44) is applied to back surfaces (52) of the IC dies (48). Each of the IC dies (48) is positioned (62) with an active surface (50) facing a support substrate (56). An encapsulant layer (72) is formed (64) overlying the laminating material (44) and the back surfaces (52) of the IC dies (48) from a molding compound (66). The molding compound (66) and the laminating material (44) are removed from the back surfaces (52) of the IC dies (48) to form (76) openings (78) exposing the back surfaces (52). Conductive material (84, 88) is placed in the openings (78) and functions as a heat sink and/or a ground for the IC dies (48).
申请公布号 US8236609(B2) 申请公布日期 2012.08.07
申请号 US20080184377 申请日期 2008.08.01
申请人 RAMANATHAN LAKSHMI N.;AMRINE CRAIG S.;XU JIANWEN;FREESCALE SEMICONDUCTOR, INC. 发明人 RAMANATHAN LAKSHMI N.;AMRINE CRAIG S.;XU JIANWEN
分类号 H01L21/56 主分类号 H01L21/56
代理机构 代理人
主权项
地址