Circuit and technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix

摘要

A circuit and technique for reducing parity bit-widths for check bit and syndrome generation is implemented through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The circuit and technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.