Sampling clock synchronizing apparatus, digital coherent receiving apparatus, and sampling clock synchronizing method

摘要

In a sampling clock synchronizing apparatus, an A/D converter converts an analog signal to a digital signal based on a sampling clock, and a processor compensates a band limitation due to spectral narrowing by filter characteristics of characteristics opposite to those of the spectral narrowing with respect to a signal produced from the A/D converter subjected to the spectral narrowing, and detects a phase shift in the sampling clock based on a signal after the compensation of the spectral narrowing and synchronizes sampling timing.