发明名称 |
Double patterning process for integrated circuit device manufacturing |
摘要 |
A method of forming an integrated circuit (IC) device feature includes forming an initially substantially planar hardmask layer over a semiconductor device layer to be patterned; forming a first photoresist layer over the hardmask layer; patterning a first set of semiconductor device features in the first photoresist layer; registering the first set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the first photoresist layer; forming a second photoresist layer over the substantially planar hardmask layer; patterning a second set of semiconductor device features in the second photoresist layer; registering the second set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the second photoresist layer; and creating topography within the hardmask layer by removing portions thereof corresponding to both the first and second sets of semiconductor device features. |
申请公布号 |
US8232210(B2) |
申请公布日期 |
2012.07.31 |
申请号 |
US20090562222 |
申请日期 |
2009.09.18 |
申请人 |
CHENG KANGGUO;YANG HAINING S.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHENG KANGGUO;YANG HAINING S. |
分类号 |
H01L21/311 |
主分类号 |
H01L21/311 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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