发明名称 POWER-OFF APPARATUS, SYSTEMS, AND METHODS
摘要 Some embodiments include apparatus, systems, and methods having a voltage generator to generate a voltage, a memory cell including a storage node associated with a storage node voltage, and a power controller to provide a signal to the voltage generator such that the voltage generated by the voltage generator rises from a voltage less than a reference voltage to a voltage less than the storage node voltage, and such that the voltage generated by the voltage generator is less than or equal to the storage node voltage, at least partially in response to the apparatus entering into a mode. Other embodiments are described.
申请公布号 US2012188831(A1) 申请公布日期 2012.07.26
申请号 US201213355841 申请日期 2012.01.23
申请人 ITO YUTAKA;DREXLER ADRIAN J.;JONES BRANDI M. 发明人 ITO YUTAKA;DREXLER ADRIAN J.;JONES BRANDI M.
分类号 G11C5/14 主分类号 G11C5/14
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