发明名称 |
Clock Data Recovery System |
摘要 |
A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal; an adder for summing the filtered data signal with a feedback signal, wherein the adder produces a summed input signal; a plurality of clocked data comparators for receiving the summed input signal, wherein the clocked data comparators determine an input data bit value; a plurality of clocked error comparators for receiving an error signal associated with clock recovery and DFE tap adaption; an equalization and adaptation logic for selecting an error sample such that a phase associated with the error sample is locked at h0=h1+h2; and a phase mixer for transmitting a delay in response to receiving the phase and the delay is transmitted to the clocked-data comparators and the clocked-error comparators. |
申请公布号 |
US2012192023(A1) |
申请公布日期 |
2012.07.26 |
申请号 |
US201213358628 |
申请日期 |
2012.01.26 |
申请人 |
LEE HAE-CHANG;JOY ANDREW KEITH;FELDMAN ARNOLD ROBERT;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
LEE HAE-CHANG;JOY ANDREW KEITH;FELDMAN ARNOLD ROBERT |
分类号 |
G06F11/07 |
主分类号 |
G06F11/07 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|