发明名称 Negative capacitance synthesis for use with differential circuits
摘要 Provided herein are methods and circuits that reduce a differential capacitance at differential nodes of a differential circuit while boosting the common mode capacitance at the differential nodes, where the differential circuit includes a pair of inputs and differential outputs. A negative capacitance is generated between differential nodes of the differential circuit, which can be accomplished by connecting a negative capacitance circuit between the differential nodes of the differential circuit. In an embodiment, the negative capacitance circuit is connected in parallel with the differential outputs of the differential circuit. In another embodiment, the negative capacitance circuit is connected in parallel with the inputs of the differential circuit. In still another embodiment, the negative capacitance circuit is connected in parallel with the differential internal nodes (i.e., nodes other than the input and output nodes) of the differential circuit.
申请公布号 US8228120(B2) 申请公布日期 2012.07.24
申请号 US20090604955 申请日期 2009.10.23
申请人 MOLE PETER J.;GOLDEN PHILIP V.;INTERSIL AMERICAS INC. 发明人 MOLE PETER J.;GOLDEN PHILIP V.
分类号 H03F3/45 主分类号 H03F3/45
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