TEST MASK SET AND MASK SET

摘要

PURPOSE: A test mask set and a mask set are provided to improve performance of a semiconductor device by purposely controlling the interval between process variables. CONSTITUTION: A plurality of gate pattern regions is arranged on a first test mask(100). One or more gate patterns are formed in each gear pattern region. A plurality of active pattern regions is arranged on a second test mask(200). One or more active patterns are formed in each active pattern region. The plurality of gate pattern regions is arranged side by side to a first direction. The plurality of active pattern regions is arranged side by side to a second direction. The first direction is perpendicular to the second direction.