| 摘要 |
<p>The disclosure describes a system and method for implementing bus operations with precise timing. The system includes a trigger descriptor register for a bus operation. The trigger descriptor register includes a bus definition field, which further includes data and address fields for providing data and address information for the bus operation. The trigger descriptor register may also include a holdoff time field to store a time value and includes an event select field to select a trigger for the bus operation. A processor configures the trigger descriptor register. A counter may count based on a time period such that at the end of the counting, the bus operation is performed based on the data and address fields. The time period is derived from one or more of the holdoff field or an external timer. The disclosed method and system employ hardware assist for maintaining precise timing while performing bus operations.</p> |
