| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide compatibility between a DDR transfer system and a bus width doubling system. <P>SOLUTION: A memory controller 16 supplies a clock CLK 1 with a first frequency to a memory 14 and a data transfer controller 18, and supplies a clock CLK 2 with a frequency twice the first frequency to the device 18. The memory controller 16 supplies data and a command to the device 18 according to the clock CLK 2. A command repeater system 20 frequency-converts the command from the controller 16 and the response from a memory 14, and supplies it to the memory 14 and the controller 16. The data repeater system 22 transmits the data from the controller 16 and data from the memory 14 through the memory 14 of the DDR transfer system, and separates data from the memory controller into two channels for the memory 14 of the bus width doubling system, and collects data for two channels from the memory into one channel. <P>COPYRIGHT: (C)2008,JPO&INPIT |
