发明名称 Scoreboard having size indicators for tracking sequential destination register usage in a multi-threaded processor
摘要 A scoreboard memory for a processing unit has separate memory regions allocated to each of the multiple threads to be processed. For each thread, the scoreboard memory stores register identifiers of registers that have pending writes. When an instruction is added to an instruction buffer, the register identifiers of the registers specified in the instruction are compared with the register identifiers stored in the scoreboard memory for that instruction's thread, and a multi-bit value representing the comparison result is generated. The multi-bit value is stored with the instruction in the instruction buffer and may be updated as instructions belonging to the same thread complete their execution. Before the instruction is issued for execution, this multi-bit value is checked. If this multi-bit value indicates that none of the registers specified in the instruction have pending writes, the instruction is allowed to issue for execution.
申请公布号 US8225076(B1) 申请公布日期 2012.07.17
申请号 US20080233515 申请日期 2008.09.18
申请人 COON BRETT W.;MILLS PETER C.;OBERMAN STUART F.;SIU MING Y.;NVIDIA CORPORATION 发明人 COON BRETT W.;MILLS PETER C.;OBERMAN STUART F.;SIU MING Y.
分类号 G06F9/30 主分类号 G06F9/30
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