Nonsequential hardware design synthesis verification

摘要

Methods and apparatuses for verifying a concurrent logical design and a corresponding non-sequential algorithmic description are provided. In some implementations, verification of a non-sequential algorithmic description for a device design is facilitated by monitoring a simulation of the non-sequential algorithmic description and synchronizing the timing of selected events with timing from an already completed simulation of a corresponding logical design. With various implementations, the hierarchical blocks in the logical design are monitored during the prior simulation to record selected event information. Subsequently, the recorded event information may be used to synchronize the simulation of the non-sequential algorithmic description.