发明名称 |
INTEGRATED CIRCUIT CHIP AND FABRICATION METHOD |
摘要 |
An electrical connection structure for an integrated circuit chip includes a through via provided in a opening and a laterally adjacent void that are formed in a rear face of a substrate die. A front face of the substrate die includes integrated circuits and a layer incorporating a front electrical interconnect network. The via extends through the substrate die to reach a connection portion of the front electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via above the void. A local external protection layer may at least partly cover the electrical connection via and the electrical connection pillar.
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申请公布号 |
US2012171877(A1) |
申请公布日期 |
2012.07.05 |
申请号 |
US201113323902 |
申请日期 |
2011.12.13 |
申请人 |
STMICROELECTRONICS (CROLLES 2) SAS |
发明人 |
CHAPELON LAURENT-LUC;CUZZOCREA JULIEN |
分类号 |
H01R12/70;H01R43/00 |
主分类号 |
H01R12/70 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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