FRACTIONAL DIGITAL PLL WITH ANALOG PHASE ERROR COMPENSATION APPARATUS

摘要

PURPOSE: A fractional digital PLP(Phase-Locked Loop) with an analog phase error compensator is provided to compensate for minute phase error detection and compensation through an analog phase error compensator by mounting the analog phase error compensator on a digital PLP. CONSTITUTION: An arithmetic operation phase error detector(110) comprises a reference accumulator(102), a high speed accumulator(104), a sampler(107), and a subtracter(103). An analog phase error compensator(200) compensates for a minute phase error value of a DCO(Digitally Controlled Oscillator) clock and a reference clock according to the minute phase difference between the reference clock and a re-timed clock. A digital loop gain controller(105) controls loop operation properties. A voltage controlled oscillator(101) changes the frequency of the DCO clock. A re-timed clock generator(106) outputs the re-timed clock by synchronizing the reference clock with the rising edge of the DCO clock.