SEMICONDUCTOR MEMORY DEVICE FOR CONTROLLING TEST MODE

摘要

PURPOSE: A semiconductor memory device controlling a test mode is provided to shorten defect analysis time by determining whether the entry of a test mode is successful. CONSTITUTION: An input unit receives a test mode setting signal. A test mode signal generating unit is connected to the input unit. A comparing unit(260) compares the test mode setting signal with the output signal of the test mode signal generating unit. A level determining unit(262) compares the test mode setting signal with the level of the test mode setting signal latched at a preset point. A combining unit(266) combines the result of the level determining unit and outputs the result.