发明名称 DESIGN SUPPORT DEVICE FOR SEMICONDUCTOR DEVICE, CAPACITOR ARRANGEMENT METHOD AND PROGRAM
摘要 <P>PROBLEM TO BE SOLVED: To solve the problem that a capacitor corresponding to the frequency characteristics of a circuit is not appropriately arranged, and that it is difficult to design a semiconductor device which is high in power supply noise resistance, and that it is necessary to insert much more capacitor cells in order to satisfy a necessary capacity. <P>SOLUTION: A design support device 1 of a semiconductor device includes: a load capacity value calculation part 103 for, on the basis of arrangement/wiring information 201 of an LSI and delay library information 202 comprising the delay element of the LSI, calculating the load capacity value of each logical cell arranged in the LSI; and a decoupling capacitor arrangement part 104 for, on the basis of the load capacity value calculated by the load capacity value calculation part 103, determining the frequency band of each logical cell, and for arranging a capacitor having frequency characteristics corresponding to the determination result in the empty area of the peripheral section of the logical cell as the object of the arrangement of the capacitor. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012123710(A) 申请公布日期 2012.06.28
申请号 JP20100275524 申请日期 2010.12.10
申请人 NEC CORP 发明人 GOTO TAKASHI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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