| 摘要 |
FIELD: information technology. ^ SUBSTANCE: adder circuit consists of separate circuits for generating output sum and carry signals based on complementary metal-oxide-semiconductor transistors, said circuits operating in parallel. To reduce delay time for generating the carry signal, the following is carried out. First, the signal from the carry circuit is not used to generate the sum signal, which reduces the capacitive load on the carry circuit. Secondly, substrates of all transistors in the carry circuit and p-type channel transistors in the sum circuit are connected to sources of these transistors, which eliminates spurious drain-substrate capacitances. Reduction of the delay time for generating the sum signal is facilitated through a circuit design solution which does not require a generated carry signal and employs series connection of two XOR circuits. ^ EFFECT: reduced delay of generating output sum and carry signals of a single-bit binary adder. ^ 3 dwg, 2 tbl |
