PURPOSE: A pipelined ADC(Analog To Digital Converter) is provided to simply perform a logical correction operation by performing a binary shift when data errors are corrected. CONSTITUTION: A conversion stage circuit(1100) includes a plurality of conversion stages(1110-11K0) which is serially connected. The conversion stage converts inputted voltages into B bits of digital codes. The conversion stage outputs residual voltages to a rear end. A digital correction circuit(1200) performs a shift operation and a logic correcting operation by adding a predetermined value to digital codes outputted from the conversion stage circuit. A clock signal generator(1300) generates clock signals necessary for a conversion operation by receiving clock voltages. A reference voltage buffer(1400) generates reference voltages necessary for the conversion operation.
申请公布号
KR20120064505(A)
申请公布日期
2012.06.19
申请号
KR20100125775
申请日期
2010.12.09
申请人
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
发明人
NAM, JAE WON;JEON, YOUNG DEUK;CHO, YOUNG KYUN;KWON, JONG KEE