Method and system for improving quality of a circuit through non-functional test pattern identification

摘要

The present invention is directed to a system and method for quality improvement by identifying test patterns for DFT logic faults and functional logic faults. The identified test patterns may be selectively utilized for pruning of patterns or DPM estimation. Functional faults and DFT faults may be identified from detected TDF faults. The functional faults are faults on a logic which was present in a pre-test insertion net list. Remaining faults are the DFT faults. A set of test patterns for DFT faults may be utilized as the first target for the pattern truncation which will reduce the amount of test patterns to be tested. A set of test patterns for functional may be utilized for improving the TDF coverage.