| 摘要 |
A encoder/decoder architecture (200, 300, 700) that uses an arithmetic encoder (220) to encode the MSB portions of the output of a Factorial Pulse Coder (212), that encodes the output of a first-level source encoder (210), e.g., MDCT. Sub-parts (e.g., frequency bands) of portions (e.g., frames) of the signal are suitably sorted in increasing order based on a measure related to signal energy (e.g., signal energy itself). Doing this in a system (100) that overlays Arithmetic Encoding on Factorial Pulse coding results in bits being re-allocated to bands with higher signal energy content, ultimately yielding higher signal quality and higher bit utilization efficiency. |
