发明名称 |
Early estimation of power consumption for electronic circuit designs |
摘要 |
In one embodiment of the invention, a method of designing integrated circuits is disclosed. The method includes determining a power correction factor for a subset of partitions of circuits in an integrated circuit design; determining a gross power consumption estimate for all partitions of circuits in the integrated circuit design without synthesizing the entire integrated circuit design; and improving the accuracy of the gross power consumption estimate using the power correction factor to generate a reasonably accurate power consumption estimate for the entire integrated circuit design prior to substantially full circuit synthesis thereof. |
申请公布号 |
US8201121(B1) |
申请公布日期 |
2012.06.12 |
申请号 |
US20080128602 |
申请日期 |
2008.05.28 |
申请人 |
SANKARALINGAM RANGANATHAN P.;MENG YAN;CADENCE DESIGN SYSTEMS, INC. |
发明人 |
SANKARALINGAM RANGANATHAN P.;MENG YAN |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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