| 摘要 |
A processor unit and a coprocessor unit are disclosed. In one embodiment, the processor unit includes a functional unit that receives a set of instructions in an instruction stream and provides the set of instructions to the coprocessor unit. The coprocessor executes the instructions and initiates transmission of a set of execution results corresponding to the set of instructions to the processor unit's functional unit. The processor functional unit may be coupled to the coprocessor unit through a shared bus circuit implementing a packet-based protocol. The processor unit and the coprocessor unit may share a coherent view of system memory. In various embodiments, the functional unit may alter entries in a translation lookaside buffer (TLB) located in the coprocessor unit, resume and suspend a thread executing on the coprocessor unit, etc. |
