| 摘要 |
<P>PROBLEM TO BE SOLVED: To prevent increase in circuit scale of a semiconductor device. <P>SOLUTION: A plurality of memory cells are specified by an X address signal and a Y address signal arranged in a matrix. A first data amplifier is connected to a first memory cell specified by a selection signal obtained by pre-decoding the Y address signal and the X address signal. A second data amplifier is connected to a second memory cell specified by a delay selection signal obtained by delaying the selection signal and the X address signal. A generation unit generates a delay operation clock signal by delaying an operation clock signal of the first data amplifier. A timing control unit accepts a first control signal for controlling operation of the first data amplifier and a second control signal for controlling operation of the second data amplifier, outputs the first control signal to the first data amplifier with timing according to the operation clock signal, and outputs the second control signal to the second data amplifier with timing according to the delay operation clock signal. <P>COPYRIGHT: (C)2012,JPO&INPIT |
