发明名称 |
Error-tolerant multi-threaded memory systems with reduced error accumulation |
摘要 |
Systems and methods establishing and/or utilizing an error-tolerant multithreaded register file are provided. The systems and methods employ dynamic multithreading redundancy (DMR) for error correction. Non-overlapped register access patterns associated create hardware redundancy dynamically that is exploited for error control. Immediate write-back and self-recovery techniques are employed to further enhance the error correction functionalities of the disclosed systems and methods. Error control is improved for memory components and processing functions in multithreaded computing systems.
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申请公布号 |
US8190982(B2) |
申请公布日期 |
2012.05.29 |
申请号 |
US20070863353 |
申请日期 |
2007.09.28 |
申请人 |
WANG LEI;UNIVERSITY OF CONNECTICUT |
发明人 |
WANG LEI |
分类号 |
G11C11/00;H03M13/00 |
主分类号 |
G11C11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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