发明名称 TEST PATTERN GENERATION DEVICE, CONTROL METHOD OF TEST PATTERN GENERATION DEVICE, AND FAILURE DETECTION DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To surely detect a delay fault of a circuit provided with a storage element. <P>SOLUTION: A current value selecting/holding section 440 selects a transition value at any time point among the transition values which transit to a forward or inverse direction according to a prescribed rule, and holds this value as a current value. A forward arithmetic section 430 calculates the transition value at the time point transited to the forward direction from the current value based on the rule. An inverse arithmetic section 420 calculates the transition value at the time point transited to the inverse direction from the current value based on the rule. An arithmetic control section 410 updates the current value held with the current value selecting/holding section 440 by the transition value calculated by the forward arithmetic section 430, and also after output to the current value selecting/holding section 440 as a first test pattern, the current value held by the current value selecting/holding section 440 is updated by the transit value calculated by the inverse arithmetic section 420 and also output to the current value selecting/holding section 440 as a second test pattern. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012098151(A) 申请公布日期 2012.05.24
申请号 JP20100246026 申请日期 2010.11.02
申请人 SONY CORP 发明人 WATANABE SHOTA
分类号 G01R31/3183;G11C29/10 主分类号 G01R31/3183
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