发明名称 SRAM CELL
摘要 The present invention provides an SRAM cell which does not have the constraints on the size of transistors in order to realize stabilized write and read operations, which has a fewer number of control signal lines per port, and which can be easily multi-ported in the read operation as well as the write operation so that the write and read operations can be performed through a single bit line. The SRAM cell includes a feedback control transistor for controlling connection or disconnection of a positive feedback circuit between particularly two inverters, a write control transistor and a read control transistor connected to a single bit line, and a read buffer transistor connected to the read control transistor.
申请公布号 US2012120717(A1) 申请公布日期 2012.05.17
申请号 US201013384648 申请日期 2010.07.02
申请人 SEKIGAWA TOSHIHIRO;MATSUMOTO YOHEI;KOIKE HANPEI;NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCEAND TECHNOLOGY 发明人 SEKIGAWA TOSHIHIRO;MATSUMOTO YOHEI;KOIKE HANPEI
分类号 G11C11/412;G11C11/419 主分类号 G11C11/412
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