发明名称 BIAS CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a bias circuit that can prevent a current variation of a current source due to a process, temperature and/or supply voltage variation. <P>SOLUTION: The bias circuit includes: a first resistor (R11) connected to a node of a third potential between a node of a first constant potential and a node of a second constant potential lower than the first constant potential; and a depletion type field effect transistor (Q11) having a drain connected to the node of the third potential via the first resistor and a gate and a source connected to the node of the second constant potential. The drain of the depletion type field effect transistor outputs a bias voltage of a first current source. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012095041(A) 申请公布日期 2012.05.17
申请号 JP20100239811 申请日期 2010.10.26
申请人 FUJITSU LTD 发明人 NAKAYA YASUHIRO
分类号 H03F1/30 主分类号 H03F1/30
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