发明名称 Bias Circuit with High Enablement Speed and Low Leakage Current
摘要 A circuit includes a first and a second PMOS transistor, wherein a gate of the second PMOS transistor is coupled to a gate and a drain of the first PMOS transistor; a first NMOS transistor having a drain coupled to a drain of the first PMOS transistor; and a second NMOS transistor, wherein a drain of the second NMOS transistor is coupled to a gate of the first NMOS transistor, a gate of the second NMOS transistor, and a drain of the second PMOS transistor. A first switch is coupled between the drain of the first PMOS transistor and the drain of the second PMOS transistor. A second switch is coupled between a source of the first NMOS transistor and an electrical ground. A third switch is coupled between a source of the second NMOS transistor and the electrical ground.
申请公布号 US2012119823(A1) 申请公布日期 2012.05.17
申请号 US20100945543 申请日期 2010.11.12
申请人 YU HUNG-CHANG;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 YU HUNG-CHANG
分类号 G05F3/02 主分类号 G05F3/02
代理机构 代理人
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