| 摘要 |
<p>A solid state circuit arrangement having a semiconductor member and presenting reduced shunt capacitances as the result of the isolation of various regions of the member from each other and a method for fabricating such arrangement by forming a subassembly of two members, constituted by a first insulating layer and the semiconductor member, by depositing one of the members on the surface of the other thereof, depositing a second insulating layer on the side of the semiconductor member which is opposite from the surface upon which the first layer bears, forming apertures in at least one of the insulating layers to expose surface portions of the semiconductor member, and etching out the portions of the semiconductor member in the region of each aperture to create cavities which extend from one of the insulating layers to the other.</p> |
