发明名称 |
METHOD AND APPARATUS FOR TESTING 3D INTEGRATED CIRCUITS |
摘要 |
A method and apparatus for testing a scan-based 3D integrated circuit (3DIC) using time-division demultiplexing/multiplexing allowing for high-data-rate scan patterns applied at input/output pads converting into low-data-rate scan patterns applied to each embeddded module in the 3DIC. A set of 3D design guidelines is proposed to reduce the number of test times and the number of through-silicon vias (TSVs) required for both pre-bond testing and post-bond testing. The technique allows reuse of scan patterns developed for pre-bond testing of each die (layer) for post-bond testing of the whole 3DIC. It further reduces test application time without concerns for I/O pad count limit and risks for fault coverage loss. |
申请公布号 |
US2012110402(A1) |
申请公布日期 |
2012.05.03 |
申请号 |
US201113222130 |
申请日期 |
2011.08.31 |
申请人 |
WANG LAUNG-TERNG;TOUBA NUR;HSIAO MICHAEL S.;WU SHIANLING;JIANG ZHIGANG;SYNTEST TECHNOLOGIES, INC. |
发明人 |
WANG LAUNG-TERNG;TOUBA NUR;HSIAO MICHAEL S.;WU SHIANLING;JIANG ZHIGANG |
分类号 |
G01R31/3177;G06F11/25 |
主分类号 |
G01R31/3177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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