发明名称 |
PREDETERMINED DUTY CYCLE SIGNAL GENERATOR |
摘要 |
Techniques for generating a signal having a predetermined duty cycle. In an exemplary embodiment, a first counter is configured to count a first number of cycles of an oscillator signal, and a second counter is configured to count a second number of cycles of the oscillator signal, with the second number being greater than the first number. The output of the second counter is used to reset the first and second counters, while the outputs of the first and second counters further drive a toggle latch for generating the signal having predetermined duty cycle. Further aspects include techniques for accommodating odd and even values for the second number. |
申请公布号 |
EP2446535(A2) |
申请公布日期 |
2012.05.02 |
申请号 |
EP20100730946 |
申请日期 |
2010.06.28 |
申请人 |
QUALCOMM INCORPORATED |
发明人 |
ZHANG, KUN;BARNETT, KENNETH CHARLES |
分类号 |
H03K5/156;H03K3/017;H03K7/06;H03K7/08;H03K21/38;H03K23/00 |
主分类号 |
H03K5/156 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|