发明名称 INSPECTION DEVICE AND INSPECTION METHOD
摘要 The present invention provides semiconductor integrated circuit, inspection device and inspection method for inspecting whether inspection target is functioning normally regardless to start-up period of a power supply voltage. The inspection device includes a reset control circuit and a tester. When a reset signal is inputted from a power-on reset circuit to a first terminal, the reset control circuit starts output of a reset execution signal having the same level as the reset signal. When a trigger signal is inputted from a control device to the second input terminal, the reset control circuit finishes the output of the reset execution signal and starts output of a release execution signal that has the same level as a reset release signal from the output terminal. The tester determines whether the power-on reset circuit is functioning normally by determining whether signals outputted from the reset control circuit are at predetermined levels.
申请公布号 US2012092038(A1) 申请公布日期 2012.04.19
申请号 US201113271607 申请日期 2011.10.12
申请人 FUJIMOTO SHUICHIRO;LAPIS SEMICONDUCTOR CO., LTD. 发明人 FUJIMOTO SHUICHIRO
分类号 G01R31/26 主分类号 G01R31/26
代理机构 代理人
主权项
地址