发明名称 |
3T HIGH DENSITY NVDRAM CELL |
摘要 |
<p>A memory circuit includes a single transistor storing both volatile and nonvolatile bit charges. The single transistor may comprise a SONOS transistor or a Floating-Gate transistor. A method of operating a combined volatile and nonvolatile memory circuit may comprise causing a first charge representing a nonvolatile bit to be stored in a charge trapping region of a transistor; and causing a second charge representing a volatile bit to be stored outside the charge trapping region of the transistor. A device may comprise a processor coupled to interact with a memory system, the memory system comprising an array of memory cells each storing a single volatile bit and a single nonvolatile bit, each cell employing a single transistor to store the volatile bit and to store the nonvolatile bit.</p> |
申请公布号 |
WO2009088909(A9) |
申请公布日期 |
2012.04.19 |
申请号 |
WO2008US88610 |
申请日期 |
2008.12.31 |
申请人 |
CYPRESS SEMICONDUCTOR CORPORATION;SCADE, ANDREAS;GUENTHER, STEFAN |
发明人 |
SCADE, ANDREAS;GUENTHER, STEFAN |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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