| 发明名称 |
MEMORY INTERFACE CONFIGURABLE FOR ASYNCHRONOUS AND SYNCHRONOUS OPERATION AND FOR ACCESSING STORAGE FROM ANY CLOCK |
| 摘要 |
An improved memory interface circuit is provided for accessing a storage array in one of two available modes, including a synchronous mode and an asynchronous mode. The improved memory interface circuit also includes logic, which enables the storage array to reside within substantially any clock domain. |
| 申请公布号 |
US2012096301(A1) |
申请公布日期 |
2012.04.19 |
| 申请号 |
US201113312929 |
申请日期 |
2011.12.06 |
| 申请人 |
CYPRESS SEMICONDUCTOR CORPORATION |
发明人 |
KHODABANDEHLOU HAMID;RAZA SYED BABAR |
| 分类号 |
G06F1/12 |
主分类号 |
G06F1/12 |
| 代理机构 |
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代理人 |
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