| 摘要 |
<P>PROBLEM TO BE SOLVED: To shorten the settling time of a phase-locked loop. <P>SOLUTION: The phase-locked loop includes: a voltage-controlled oscillator for generating an oscillation signal including an oscillation frequency depending on a control signal; a divider for dividing the frequency of the oscillation signal to generate a frequency-divided signal; a phase comparator for comparing the phase of the frequency-divided signal with the phase of a reference signal to generate a comparison signal; a charge pump for outputting a current depending on the comparison signal; a filter for filtering the current to generate the control signal; a frequency difference detection circuit for generating a detection signal when a difference between the value of a constant multiple of the frequency of the frequency-divided signal and the value of a constant multiple of the frequency of the reference signal is a minimum; and a phase adjustment circuit for synchronizing the phase of the frequency-divided signal with the phase of the reference signal when the detection signal is generated. <P>COPYRIGHT: (C)2012,JPO&INPIT |
