Scheckabrechnungsmaschine

摘要

1,196,260. Digital calculators; delay line stores. INTERNATIONAL BUSINESS MACHINES CORP. 20 Dec., 1967 [30 Dec., 1966], No. 57990/67. Headings G4A and G4C. In data processing apparatus, a keyboard feeds a one-field "entry" recirculating delay line store, and a timing ring selects a field of a multifield "main" recirculating delay line store, the contents of the entry store and the selected field of the main store being added and the result inserted into the selected field of the main store. In a bank machine, decimal digits from a keyboard (entered high order first) are coded in BCD form by OR gates, stored in entry latches, then serialized by gates and inserted into a recirculating entry delay line loop. The loop comprises a delay line capable of holding a field of ten digits, retiming triggers, and a one-digit shift register which is normally by-passed. Arrival of a digit in the entry latches causes digits already in the loop to be recirculated via the shift register for one revolution and the new digit to be inserted in front of them in the loop. A "double zero" key on the keyboard causes zero to be entered twice, by delaying reset of the entry latches (which normally occurs after each digit) until a zero entered into them has been inserted into the delay loop twice. The field in the entry delay loop can be passed low order first, serially by digit, parallel by bit, from the shift register to an adder to be added to any of twenty fields from a main delay loop, this loop comprising a delay line and a one-digit shift register for supplying the field to the adder in serial-parallel form. Manual selector keys controlling latches which control pluggable programme cards can select main loop fields for this, and the stackers to which cheques are to be directed. The adder comprises in order: conversion from BCD to qui-binary (by gates), complementing of the main loop operand digits if the operand signs are different or if a subtraction is required (e.g. to check a sum of cheque amounts against a deposit slip total), qui-binary addition, conversion from qui-binary to BCD, latching of the result digit, and serializing (by gates) for insertion of the result into the main loop source field. When complementing took place, recomplementing or end-around add follows as necessary, utilizing a marker bit stored in the main loop. The various main loop fields can be printed out, on three printers, in response to keys or detection of non-balance in the check referred to. Marker bits may be stored in the main loop to indicate fields already printed when a sequence of fields is being printed. The delay lines may be of the magnetostrictive or sonic type. Specification 1,196,259 is referred to.