| 摘要 |
PURPOSE: A cryptographic apparatus and memory system are provided to increase the speed of a cryptographic process by parallely performing an encryption process. CONSTITUTION: A cryptographic apparatus(10) includes code cores(20-1-20-4) and a code operation control unit(30). The code core uses key data inputted through a key data signal line(41). Each code core performs the calculation of a symmetric key encryption algorithm for input data inputted through the code operation control unit. The code core parallely encodes a plurality of input data blocks successively inputted through the code operation control unit. The key data signal line is connected to an interface unit. Key data is inputted to the code core from the interface unit through the key data signal line. |
