| 发明名称 |
Low Read Current Architecture For Memory |
| 摘要 |
A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured. |
| 申请公布号 |
US2012075914(A1) |
申请公布日期 |
2012.03.29 |
| 申请号 |
US201113252934 |
申请日期 |
2011.10.04 |
| 申请人 |
BATEMAN BRUCE;RINERSON DARRELL;CHEVALLIER CHRISTOPHE;SIAU CHANG HUA;UNITY SEMICONDUCTOR CORPORATION |
发明人 |
BATEMAN BRUCE;RINERSON DARRELL;CHEVALLIER CHRISTOPHE;SIAU CHANG HUA |
| 分类号 |
G11C11/00 |
主分类号 |
G11C11/00 |
| 代理机构 |
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代理人 |
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| 主权项 |
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