| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a serial communication apparatus including an interface circuit having a transmitter-receiver circuit that communicates with an internal circuit using a predetermined synchronous clock and a PLL circuit that generates the synchronous clock based on a reference clock to be input, thus preventing erroneous operations of the interface circuit and the internal circuit. <P>SOLUTION: A delay circuit 5 delays a reset signal PERST# generated after a frequency of a reference clock REFCLK is stable at 100 MHz by a predetermined delay time Δt to generate an internal reset signal PERST2 and outputs the signal to a link controller 31. A PHY circuit 2 is reset in response to the reset signal PERST#, and the link controller 31 is reset in response to the internal reset signal PERST2. Also, the delay time Δt is set to be longer than a lock-up time previously calculated based on a circuit specification of a PLL circuit 23. <P>COPYRIGHT: (C)2012,JPO&INPIT |
