发明名称 Method for Control of Solder Collapse in Stacked Microelectronic Structure
摘要 A process and product made from the process is disclosed to minimize solder collapse during solder reflow. Predetermined bond pads on a layer or component have a solder paste such as Sn63 solder paste with a first lower reflow temperature applied and a spacer element such as an SAC solder ball or stud bump having a predetermined geometry with a second higher reflow temperature applied. The SAC solder balls or stud bumps act as spacing elements but do not interact with the solder paste such that the solder paste may be reflowed while precisely maintaining the space between the layers.
申请公布号 US2012069528(A1) 申请公布日期 2012.03.22
申请号 US201113209933 申请日期 2011.08.15
申请人 BINDRUP RANDY;YAMAGUCHI JAMES;BOYD W. ERIC;IRVINE SENSORS CORPORATION 发明人 BINDRUP RANDY;YAMAGUCHI JAMES;BOYD W. ERIC
分类号 H05K7/00;B23K1/20 主分类号 H05K7/00
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