| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a delay locked loop capable of increasing an operating frequency of a DRAM even when a frequency of an input clock increases, by ensuring operating margin that can generate a rising/polling out enable signal R/FOUTEN by a second DLL clock FCLK_DLLOE. <P>SOLUTION: An output driver comprises: a first driving section that receives a clock output from a delay locked loop, generates a first DLL clock used for outputting read data, and drives with a first timing delay; and a second driving section that receives the clock output from the delay locked loop, generates a second DLL clock used for reducing current consumption during a write operation, and drives with a second timing delay smaller than the first timing delay. <P>COPYRIGHT: (C)2012,JPO&INPIT |
